Introduction to 1OMAP5912 Platform The services provided by DSP/BIOS LINK for developers are: basic processor control (start, execute, stop), logical channel (CHANNEL) based data transfer, and message (based on MSGQ module). It consists of three components: PROC, CHNL, and MSGQ. PROC is the abbreviation of PROCESSCONTROL. It is responsible for the operation of the DSP processor in the user space of the application. The main functions are: DSP initialization, loading, execution and stop of the DSP program. CHNL is an abbreviation of CHANNEL, which represents the logical channel of data flow between ARM and DSP, and is responsible for data transmission between ARM and DSP. CHNL is a logical entity between ARM and DSP that implements the physical connection between the two. MSGQ is the abbreviation of MESSAGEQUEUE, which is responsible for the interaction and communication of messages of different lengths between ARM and DSP. The reception and transmission of messages is implemented through the message queue [4].
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The open multimedia application platform ((pen MuITImedia Appli-caTIons PIatform, OMAP) is a high-performance multimedia processor developed for third-generation mobile phones. In addition to the performance/power ratio advantages, it also provides a rich peripheral interface that supports almost all popular wired and wireless interface standards. Because of its outstanding performance, the platform has always been favored by the world's major mobile device manufacturers (such as Nokia, Ericsson, Sony, etc.).
The 0MAP5912 features a unique dual-core architecture with a processor with TI-enhanced ARM926EJ-S core for control and a high-performance, low-power TMS320C55x DSP core for data processing. The ARM processor can be used to implement various communication protocols, controls, and human-machine interfaces; the DSP has multiple data address buses, which is ideal for data-intensive multimedia processing (such as video codec) and has extremely low power consumption [l]. In order to combine the advantages of these two processors to maximize their efficiency, the dual-core communication mechanism plays a crucial role.
2 OMAP5912 dual-core communication method
There are two kinds of shared mailbox registers and shared storage space in ARM and DSP dual-core communication modes in 0MAP5912. In practice, these dual-core communication methods need to be used together. For example, in the dual-core communication, the handshake is small, and the shared message can be used to transmit the message in a timely and reliable manner. When a large amount of data (such as image data) needs to be transmitted, it is usually necessary to use a highly efficient shared storage space. .
2.1 shared mailbox register mode
The dual cores can interrupt each other and pass a small amount of data through the mailbox register. There are 4 sets of mailbox registers, each set of mailbox registers consists of 2 16-bit registers and 1 1-bit register. When a processor writes the appropriate command word to the command word register, the register generates an interrupt and the flag register of the other processor is properly set. The interrupted processor responds to the interrupt by reading the flag register and clears the flag register. Each set of mailbox registers also has an additional data word register that transfers 2 words of data between processors at each interrupt. The information communicated through commands and data words is completely user defined. Data words can be used to represent address pointers or status words.
2.2 shared memory mode
There are two ways to share memory. In the first way, ARM obtains access to the DSP storage space and I/O space through the host interface (MPUI Interface, MPUI), and the data is moved between the dual cores by the ARM. The MPUI provides a bridge between the MPU and the system DMA controller to communicate with the DSP and its peripherals. The MPuI provides access to the entire memory space of the DSP and its common peripheral bus.
Another way is that the ARM maps the external storage space of the DSP to the OMAP5912 system storage resource by setting the DSP Memory Management Unit (MMU), and the DSP completes the data transmission between the dual cores. The OMAP5912 implements shared memory through a Traffic Controller (TC), so that ARM and DSP can access shared static random access memory (StaTIcRAM, SRAM), high-speed external memory interface (I, Zxteraaal: Mem0ry Interface Fast, EMIFF) and low-speed external memory. Ex-terhal Memory Interface Slow (EMIFS) storage space [2].
3 Basic application for communication between dual cores
In order to reduce the difficulty of implementation of upper-layer application developers and save design time, the basic application of dual-core communication--DSP/BIOSLINK[3] is adopted, which is the realization of the above two dual-core communication methods. Developers only need to use the interface functions provided by DSP/BIOSLINK when doing upper-level application development. DSP/BIOS LINK allows developers to access and control the DSP's operating environment on the ARM side using a standard set of APIs; for asymmetric, processor environments consisting of one general purpose processor (such as ARM) and one or more DSPs. Figure 1 shows the software architecture of DSP/BIOSLINK. 
4 OMAP5912 based digital audio system buy
The author introduces the specific application of OMAP dual-core communication by taking the digital audio system based on OMAP5912_ as an example. The system is implemented on the basis of RF6 (ReferenceFramework Level 6) framework. The whole system converts the input stereo audio signal into left and right two-channel data frames according to the given sampling rate and quantization precision, and then performs finite impulse filter FIR on it. The algorithm and sound control VOL algorithm processes and then synthesizes the stereo output. The whole system is divided into two parts: the ARM-side application and the DSP-side algorithm.
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